A field programmable gate array (FPGA) is a semiconductor device that allows a user side to freely set (program) the arrangement of pins, I/O signals allocated to the pins and a circuit configuration. For input/output (IO) signals, a standard (LVTTL (low-voltage TTL)/LVCMOS (low-voltage CMOS)/HSTL (high-speed transceiver logic), or the like), an output current value (12 mA/8 mA/4 mA, or the like), and slew rate control (FAST/SLOW) may be set at the user side. For this reason, considerably flexible design may be performed.
When I/O signals allocated to the pins simultaneously operate, noise called SSO (Simultaneous Switching Output) noise is generated. The SSO noise propagates into the FPGA, and induces erroneous operation of a circuit configured in the FPGA. For this reason, to cause the FPGA to appropriately operate, that is, to appropriately perform the design for the FPGA, it is also presumably important that not only the amount of generated SSO noise is estimated but also the influence of SSO noise on the circuit is estimated quantitatively. In addition, it is also important to appropriately reflect the estimated result on the design (programming).
In the FPGA, with an increase in the number of pins or an increase in speed of circuit operation, the degree of influence of SSO noise have been further increasing. With the above background, it is presumably highly important to appropriately handle SSO noise in the future.    [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2005-4245.